One of the most common devices to include a sensor array is an image sensor, which has an array of pixels that convert optical signals into electrical analog signals. These analog signals must be transferred off chip, often after being converted into a digital signal. There are a number of problems associated with this process mainly involving limiting power consumption, noise, and die area while increasing the speed at which data can be conveyed off chip.
In addition to image sensors which involve conversion between optical signals and electrical signals, there are a large number of different sensing elements which require conversion of signals from one type to another type. Some examples of these are elements dealing with acoustic waves, electromagnetic waves including radio waves, IR, X-rays and others, mechanical properties and chemical properties. The conversion of these properties is generally performed by using transducers, detectors and sensors. Photodetectors, X-ray detectors, thermo-detectors, IR detectors, radiation detectors, capacitive sensors and the likes generate electrical analog signals in response to electromagnetic waves which impinge upon them. Acoustic detectors detect acoustic waves and generate electrical analog signals. Mechanical transducers, on the other hand, measure mechanical properties such as, strain, displacement, flatness, and others and often produce electrical signals.
In this specification, the invention is described in detail in connection with optical image sensors but it should be noted that the concept of the invention is equally applicable to other fields some of which are mentioned above.
Certain image sensor architectures consume a large amount of power. The addition of features such as analog to digital converters (ADC) made feasible by CMOS image sensor technology only serves to increase the power consumption. Noise is also a major concern. Fixed pattern noise (FPN) caused by non-uniformities in the sensor array and local signal path (i.e. imperfect matching of transistor properties across the die), capacitor noise, and switching noise must all be taken into consideration. The high resolution and fast scanning rates of today's imagers also cause the speed of the output path to become a significant issue. A number of factors combine to reduce the rate at which data can be transferred off chip. The large size of the array implies a need to drive long busses with large parasitic capacitances. As well, the small pixel size results in the column amplifiers being confined to a narrow pitch, and therefore having a small current driving capability.
Solutions to these concerns do exist but they usually result in a large die area penalty. If the die area occupied by the proposed solutions is too large, it will compromise the economic viability of the design.
In U.S. Pat. No. 5,892,540 Apr. 6, 1999 Kozlowski et al, low noise amplifiers for passive pixel CMOS imagers are described. It uses capacitive transimpedance amplifier with gain-setting feedback capacitors and selectable load capacitors.
Charge couple devices (CCD) and early CMOS image sensors did not integrate an ADC on chip. These devices produced an analog output voltage and therefore require an additional IC to perform the conversion to a digital signal. Extra IC's are costly and inhibit the miniaturization of camera systems.
The integration of ADCs is one of the key advantages of CMOS image sensor technology. There are a number of current techniques for implementing an integrated ADC. A single ADC per chip has a number of advantages in that it introduces little noise to the system and consumes less power than other techniques. The major advantage of this technique is the significant reduction in die area it offers in comparison to other configurations of integrated ADCs. However, a single ADC places a significant bottleneck in the output path which needs to be addressed in order for fast pixel rates to be maintained. The bottleneck issue becomes more prominent as array sizes continue to grow.
Column parallel ADCs are one solution to this bottleneck. By implementing one ADC per column, a large amount of data can be quickly digitized. However, column parallel ADCs result in an extremely large die area penalty. In fact, ADCs arranged in this manner can take up nearly as much die area as the sensor array itself. Column parallel ADCs also introduce a serious amount of noise to the system. Not only is the amount of switching noise increased, but also column to column noise is introduced by process variations between the different ADCs.
Yet another solution is the use of pixel level ADCs where an ADC is implemented as a part of each pixel cell. This solution has the advantages of high speed and a high signal to noise ratio. Unfortunately, this technology results in a large pixel size and low fill factor which limit the possible resolution of the sensor. As each pixel containing an ADC will logically consume more power than those that do not, arrays using pixel level ADC technology will be limited in size by their power consumption.
Followings are some prior art technologies dealing with CMOS imagers and problems associated with them. U.S. Pat. No. 5,920,274 Jul. 6, 1999 Gowda et al describes a column parallel ADC architecture employing non-uniform A/D conversion. U.S. Pat. No. 5,917,547 Jun. 29, 1999 Merrill et al, on the other hand, describes a two-stage amplifier for active pixel sensor cell array for reducing fixed pattern noise in the array output.
The present invention addresses above-mentioned difficulties of the prior art technologies. It provides a novel electrical sensing apparatus and method which are characterized in a low power, low noise, and analog output path which occupies minimal die area while maintaining certain data rates. If a product design requires ADCs, the invention ensures a minimal number of ADCs in the output path and this vastly reduces the power consumption and switching noise on the device as well as having notable die area benefits. A two stage pipeline architecture of the invention maintains fast pixel rates with this minimal ADC arrangement.
The two stage pipeline architecture without the use of ADCs can be also implemented in a device where analog outputs off chip are desired. The pipelining signals from the first stage amplifiers in this implementation realizes similar benefits to those mentioned above.